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Dual-Channel Digital Isolator, Enhanced System-Level ESD Reliability ADUM3210
FEATURES
Enhanced system-level ESD performance per IEC 61000-4-x High temperature operation: 125C Default low output Narrow body, RoHS-compliant, 8-lead SOIC Low power operation 5 V operation 1.6 mA per channel maximum @ 0 Mbps to 2 Mbps 3.7 mA per channel maximum @ 10 Mbps 3 V operation 1.4 mA per channel maximum @ 0 Mbps to 2 Mbps 2.4 mA per channel maximum @ 10 Mbps 3 V/5 V level translation High data rate: dc to 10 Mbps (NRZ) Precise timing characteristics 3 ns maximum pulse width distortion 3 ns maximum channel-to-channel matching High common-mode transient immunity: >25 kV/s Safety and regulatory approvals UL recognition: 2500 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice #5A VDE Certificate of Conformity DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 VIORM = 560 V peak
GENERAL DESCRIPTION
The ADUM32101 is a dual-channel, digital isolator based on Analog Devices, Inc., iCoupler(R) technology. Combining high speed CMOS and monolithic transformer technology, this isolation component provides outstanding performance characteristics superior to alternatives such as optocoupler devices. By avoiding the use of LEDs and photodiodes, iCoupler devices remove the design difficulties commonly associated with optocouplers. The typical optocoupler concerns regarding uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects are eliminated with the simple iCoupler digital interfaces and stable performance characteristics. The need for external drivers and other discrete components is eliminated with these iCoupler products. Furthermore, iCoupler devices consume one-tenth to onesixth the power of optocouplers at comparable signal data rates. The ADUM3210 isolator provides two independent isolation channels. It operates with the supply voltage on either side ranging from 2.7 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling voltage translation functionality across the isolation barrier. The ADUM3210 has a default output low characteristic in comparison to the ADuM3200/ADuM3201 models that have a default output high characteristic. The ADUM3210 is also available in 125C temperature grade. In comparison to the ADuM1210 isolator, the ADUM3210 isolator contains various circuit and layout changes providing increased capability relative to system-level IEC 61000-4-x testing (ESD, burst, and surge). The precise capability in these tests for either the ADuM1210 or ADUM3210 products is strongly determined by the design and layout of the user's board or module. For more information, see AN-793 Application Note, ESD/Latch-Up Considerations with iCoupler Isolation Products.
APPLICATIONS
Size-critical multichannel isolation Plasma display panels
FUNCTIONAL BLOCK DIAGRAM
VDD1 1 VIA 2 VIB 3 GND1 4 ENCODE ENCODE
ADUM3210
DECODE DECODE
8
VDD2 VOA VOB GND2
06866-001
7
6
5
Figure 1.
1
Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,239. Other patents pending.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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ADUM3210 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Characteristics--5 V, 105C and 125C Operation....................................................................................... 3 Electrical Characteristics--3 V, 105C Operation..................... 4 Electrical Characteristics--3 V, 125C Operation..................... 5 Electrical Characteristics--Mixed 5 V/3 V or 3 V/5 V, 105C Operation ........................................................................... 6 Electrical Characteristics--Mixed 5 V/3 V or 3 V/5 V, 125C Operation ........................................................................... 8 Package Characteristics ............................................................. 10 Regulatory Information ............................................................. 10 Insulation and Safety-Related Specifications .......................... 10 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics ............................................................................ 11 Recommended Operating Conditions .................................... 11 Absolute Maximum Ratings ......................................................... 12 ESD Caution................................................................................ 12 Pin Configuration and Function Descriptions........................... 13 Typical Performance Characteristics ........................................... 14 Applications Information .............................................................. 15 PC Board Layout ........................................................................ 15 System-Level ESD Considerations and Enhancements ........ 15 Propagation Delay-Related Parameters ................................... 15 DC Correctness and Magnetic Field Immunity........................... 15 Power Consumption .................................................................. 16 Insulation Lifetime ..................................................................... 17 Outline Dimensions ....................................................................... 18 Ordering Guide .......................................................................... 18
REVISION HISTORY
9/08--Rev. Sp0 to Rev. A Changes to Features and General Description Sections.............. 1 Changes to Specifications Section .................................................. 3 Changes to Recommended Operating Conditions Section ...... 11 Changes to Ordering Guide .......................................................... 18 7/07--Revision Sp0: Initial Version
Rev. A | Page 2 of 20
ADUM3210 SPECIFICATIONS
ELECTRICAL CHARACTERISTICS--5 V, 105C AND 125C OPERATION
All voltages are relative to their respective ground. 4.5 V VDD1 5.5 V, 4.5 V VDD2 5.5 V. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25C, VDD1 = VDD2 = 5 V. Table 1.
Parameter DC SPECIFICATIONS Input Supply Current, per Channel, Quiescent Output Supply Current, per Channel, Quiescent ADUM3210, Total Supply Current, Two Channels 1 DC to 2 Mbps VDD1 Supply Current VDD2 Supply Current 10 Mbps VDD1 Supply Current VDD2 Supply Current Input Currents Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages Symbol IDDI (Q) IDDO (Q) Min Typ 0.4 0.5 Max 0.8 0.6 Unit mA mA Test Conditions
IDD1 (Q) IDD2 (Q) IDD1 (10) IDD2 (10) IIA, IIB VIH VIL VOAH VOBH
1.3 1.0 3.5 1.7 +0.01
1.7 1.6 4.6 2.8 +10
mA mA mA mA A V V V V
DC to 1 MHz logic signal freq. DC to 1 MHz logic signal freq. 5 MHz logic signal freq. 5 MHz logic signal freq. 0 VIA, VIB VDD1 or VDD2
-10 0.7 x (VDD1 or VDD2) (VDD1 or VDD2) - 0.1 (VDD1 or VDD2) - 0.5
0.3 x (VDD1 or VDD2) 5.0 4.8 0.0 0.04 0.2 0.1 0.1 0.4 100 10 20 5 50 3 15 3 25 25 2.5 35 35 1.2 0.19 0.05
IOx = -20 A, VIx = VIxH IOx = -4 mA, VIx = VIxH IOx = 20 A, VIx = VIxL IOx = 400 A, VIx = VIxL IOx = 4 mA, VIx = VIxL CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels VIx = VDD1, VDD2, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Logic Low Output Voltages
VOAL VOBL
V V V ns Mbps ns ns ps/C ns ns ns kV/s kV/s Mbps mA/Mbps mA/Mbps
SWITCHING SPECIFICATIONS Minimum Pulse Width 2 Maximum Data Rate 3 Propagation Delay 4 Pulse Width Distortion, |tPLH - tPHL|4 Change vs. Temperature Propagation Delay Skew 5 Channel-to-Channel Matching 6 Output Rise/Fall Time (10% to 90%) Common-Mode Transient Immunity at Logic High Output 7 Common-Mode Transient Immunity at Logic Low Output7 Refresh Rate Input Dynamic Supply Current, per Channel 8 Output Dynamic Supply Current, per Channel8
1
PW tPHL, tPLH PWD tPSK tPSKCD tR/tF |CMH| |CML| fr IDDI (D) IDDO (D)
The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 4 through Figure 6 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 7 and Figure 8 for total VDD1 and VDD2 supply currents as a function of data rate. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 4 through Figure 6 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate. Rev. A | Page 3 of 20
ADUM3210
ELECTRICAL CHARACTERISTICS--3 V, 105C OPERATION
All voltages are relative to their respective ground. 2.7 V VDD1 3.6 V, 2.7 V VDD2 3.6 V. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25C, VDD1 = VDD2 = 3.0 V. Table 2.
Parameter DC SPECIFICATIONS Input Supply Current, per Channel, Quiescent Output Supply Current, per Channel, Quiescent ADUM3210BR, Total Supply Current, Two Channels 1 DC to 2 Mbps VDD1 Supply Current VDD2 Supply Current 10 Mbps VDD1 Supply Current VDD2 Supply Current Input Currents Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages Symbol IDDI (Q) IDDO (Q) Min Typ 0.3 0.3 Max 0.5 0.5 Unit mA mA Test Conditions
IDD1 (Q) IDD2 (Q) IDD1 (10) IDD2 (10) IIA, IIB VIH VIL VOAH VOBH (VDD1 or VDD2) - 0.1 (VDD1 or VDD2) - 0.5
0.8 0.7 2.0 1.1 +0.01
1.3 1.0 3.2 1.7 +10
mA mA mA mA A V V V V
DC to 1 MHz logic signal freq. DC to 1 MHz logic signal freq. 5 MHz logic signal freq. 5 MHz logic signal freq. 0 VIA, VIB, VDD1 or VDD2
-10 0.7 x (VDD1 or VDD2)
0.3 x (VDD1 or VDD2) 3.0 2.8 0.0 0.04 0.2 0.1 0.1 0.4 100 10 20 5 60 3 22 3 25 25 3.0 35 35 1.1 0.10 0.03
IOx = -20 A, VIx = VIxH IOx = -4 mA, VIx = VIxH IOx = 20 A, VIx = VIxL IOx = 400 A, VIx = VIxL IOx = 4 mA, VIx = VIxL CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels VIx = VDD1, VDD2, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Logic Low Output Voltages
VOAL VOBL
V V V ns Mbps ns ns ps/C ns ns ns kV/s kV/s Mbps mA/Mbps mA/Mbps
SWITCHING SPECIFICATIONS Minimum Pulse Width 2 Maximum Data Rate 3 Propagation Delay 4 Pulse Width Distortion, |tPLH - tPHL|4 Change vs. Temperature Propagation Delay Skew 5 Channel-to-Channel Matching 6 Output Rise/Fall Time (10% to 90%) Common-Mode Transient Immunity at Logic High Output 7 Common-Mode Transient Immunity at Logic Low Output7 Refresh Rate Input Dynamic Supply Current, per Channel 8 Output Dynamic Supply Current, per Channel8
1
PW tPHL, tPLH PWD tPSK tPSKCD tR/tF |CMH| |CML| fr IDDI (D) IDDO (D)
The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 4 through Figure 6 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 7 and Figure 8 for total VDD1 and VDD2 supply currents as a function of data rate. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 4 through Figure 6 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate. Rev. A | Page 4 of 20
ADUM3210
ELECTRICAL CHARACTERISTICS--3 V, 125C OPERATION
All voltages are relative to their respective ground. 3.0 V VDD1 3.6 V, 3.0 V VDD2 3.6 V. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25C, VDD1 = VDD2 = 3.0 V. Table 3.
Parameter DC SPECIFICATIONS Input Supply Current, per Channel, Quiescent Output Supply Current, per Channel, Quiescent ADUM3210TR, Total Supply Current, Two Channels 1 DC to 2 Mbps VDD1 Supply Current VDD2 Supply Current 10 Mbps VDD1 Supply Current VDD2 Supply Current Input Currents Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages Symbol IDDI (Q) IDDO (Q) Min Typ 0.3 0.3 Max 0.5 0.5 Unit mA mA Test Conditions
IDD1 (Q) IDD2 (Q) IDD1 (10) IDD2 (10) IIA, IIB VIH VIL VOAH VOBH (VDD1 or VDD2) - 0.1 (VDD1 or VDD2) - 0.5
0.8 0.7 2.0 1.1 +0.01
1.3 1.0 3.2 1.7 +10
mA mA mA mA A V V V V
DC to 1 MHz logic signal freq. DC to 1 MHz logic signal freq. 5 MHz logic signal freq. 5 MHz logic signal freq. 0 VIA, VIB, VDD1 or VDD2
-10 0.7 x (VDD1 or VDD2)
0.3 x (VDD1 or VDD2) 3.0 2.8 0.0 0.04 0.2 0.1 0.1 0.4 100 10 20 5 60 3 22 3 25 25 3.0 35 35 1.1 0.10 0.03
IOx = -20 A, VIx = VIxH IOx = -4 mA, VIx = VIxH IOx = 20 A, VIx = VIxL IOx = 400 A, VIx = VIxL IOx = 4 mA, VIx = VIxL CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels VIx = VDD1, VDD2, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Logic Low Output Voltages
VOAL VOBL
V V V ns Mbps ns ns ps/C ns ns ns kV/s kV/s Mbps mA/Mbps mA/Mbps
SWITCHING SPECIFICATIONS Minimum Pulse Width 2 Maximum Data Rate 3 Propagation Delay 4 Pulse Width Distortion, |tPLH - tPHL|4 Change vs. Temperature Propagation Delay Skew 5 Channel-to-Channel Matching 6 Output Rise/Fall Time (10% to 90%) Common-Mode Transient Immunity at Logic High Output 7 Common-Mode Transient Immunity at Logic Low Output7 Refresh Rate Input Dynamic Supply Current, per Channel 8 Output Dynamic Supply Current, per Channel8
1
PW tPHL, tPLH PWD tPSK tPSKCD tR/tF |CMH| |CML| fr IDDI (D) IDDO (D)
The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 4 through Figure 6 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 7 and Figure 8 for total VDD1 and VDD2 supply currents as a function of data rate. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 4 through Figure 6 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate. Rev. A | Page 5 of 20
ADUM3210
ELECTRICAL CHARACTERISTICS--MIXED 5 V/3 V OR 3 V/5 V, 105C OPERATION
All voltages are relative to their respective ground. 5 V/3 V operation: 4.5 V VDD1 5.5 V, 2.7 V VDD2 3.6 V. 3 V/5 V operation: 2.7 V VDD1 3.6 V, 4.5 V VDD2 5.5 V. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25C; VDD1 = 3.0 V, VDD2 = 5.0 V; or VDD1 = 5.0 V, VDD2 = 3.0 V. Table 4.
Parameter DC SPECIFICATIONS Input Supply Current, per Channel, Quiescent 5 V/3 V Operation 3 V/5 V Operation Output Supply Current, per Channel, Quiescent 5 V/3 V Operation 3 V/5 V Operation ADUM3210BR, Total Supply Current, Two Channels 1 DC to 2 Mbps VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation 10 Mbps VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation Input Currents Logic High Input Threshold Logic Low Input Threshold 5 V/3 V Operation 3 V/5 V Operation Logic High Output Voltages Symbol IDDI (Q) 0.4 0.3 IDDO (Q) 0.3 0.5 0.5 0.6 mA mA 0.8 0.5 mA mA Min Typ Max Unit Test Conditions
IDD1 (Q) 1.3 0.8 IDD2 (Q) 0.7 1.0 IDD1 (10) 3.5 2.0 IDD2 (10) 1.1 1.7 +0.01 1.7 2.8 +10 mA mA A V V V V V V 0.1 0.1 0.4 100 10 15 5 tPSK tPSKCD tR/tF 3.0 2.5 22 3 55 3 V V V ns Mbps ns ns ps/C ns ns ns ns 5 MHz logic signal freq. 5 MHz logic signal freq. 0 VIA, VIB VDD1 or VDD2 4.6 3.2 mA mA 5 MHz logic signal freq. 5 MHz logic signal freq. 1.0 1.6 mA mA DC to 1 MHz logic signal freq. DC to 1 MHz logic signal freq. 1.7 1.3 mA mA DC to 1 MHz logic signal freq. DC to 1 MHz logic signal freq.
IIA, IIB VIH VIL
-10 0.7 x (VDD1 or VDD2)
0.3 x (VDD1 or VDD2) 0.8 0.4 (VDD1 or VDD2) - 0.1 (VDD1 or VDD2) - 0.5
VOAH, VOBH
Logic Low Output Voltages
VOAL, VOBL
(VDD1 or VDD2) VDD1, VDD2 - 0.2 0.0 0.04 0.2
IOx = -20 A, VIx = VIxH IOx = -4 mA, VIx = VIxH IOx = 20 A, VIx = VIxL IOx = 400 A, VIx = VIxL IOx = 4 mA, VIx = VIxL CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels
SWITCHING SPECIFICATIONS Minimum Pulse Width 2 Maximum Data Rate 3 Propagation Delay 4 Pulse Width Distortion, |tPLH - tPHL|4 Change vs. Temperature Propagation Delay Skew 5 Channel-to-Channel Matching 6 Output Rise/Fall Time (10% to 90%) 5 V/3 V Operation 3 V/5 V Operation
PW tPHL, tPLH PWD
Rev. A | Page 6 of 20
ADUM3210
Parameter Common-Mode Transient Immunity at Logic High Output 7 Common-Mode Transient Immunity at Logic Low Output7 Refresh Rate 5 V/3 V Operation 3 V/5 V Operation Input Dynamic Supply Current, per Channel 8 5 V/3 V Operation 3 V/5 V Operation Output Dynamic Supply Current, per Channel8 5 V/3 V Operation 3 V/5 V Operation
1
Symbol |CMH| |CML| fr
Min 25 25
Typ 35 35
Max
Unit kV/s kV/s
Test Conditions VIx = VDD1, VDD2, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
1.2 1.1 IDDI (D) 0.19 0.10 IDDO (D) 0.03 0.05
Mbps Mbps mA/Mbps mA/Mbps mA/Mbps mA/Mbps
The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 4 through Figure 6 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 7 and Figure 8 for total VDD1 and VDD2 supply currents as a function of data rate. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 4 through Figure 6 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate.
Rev. A | Page 7 of 20
ADUM3210
ELECTRICAL CHARACTERISTICS--MIXED 5 V/3 V OR 3 V/5 V, 125C OPERATION
All voltages are relative to their respective ground. 5 V/3 V operation: 4.5 V VDD1 5.5 V, 3.0 V VDD2 3.6 V. 3 V/5 V operation: 3.0 V VDD1 3.6 V, 4.5 V VDD2 5.5 V. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25C; VDD1 = 3.0 V, VDD2 = 5.0 V; or VDD1 = 5.0 V, VDD2 = 3.0 V. Table 5.
Parameter DC SPECIFICATIONS Input Supply Current, per Channel, Quiescent 5 V/3 V Operation 3 V/5 V Operation Output Supply Current, per Channel, Quiescent 5 V/3 V Operation 3 V/5 V Operation ADUM3210TR, Total Supply Current, Two Channels 1 DC to 2 Mbps VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation 10 Mbps VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation Input Currents Logic High Input Threshold Logic Low Input Threshold 5 V/3 V Operation 3 V/5 V Operation Logic High Output Voltages Symbol IDDI (Q) 0.4 0.3 IDDO (Q) 0.3 0.5 0.5 0.6 mA mA 0.8 0.5 mA mA Min Typ Max Unit Test Conditions
IDD1 (Q) 1.3 0.8 IDD2 (Q) 0.7 1.0 IDD1 (10) 3.5 2.0 IDD2 (10) 1.1 1.7 +0.01 1.7 2.8 +10 mA mA A V V V V V V 0.1 0.1 0.4 100 10 15 5 tPSK tPSKCD tR/tF 3.0 2.5 22 3 55 3 V V V ns Mbps ns ns ps/C ns ns ns ns 5 MHz logic signal freq. 5 MHz logic signal freq. 0 VIA, VIB VDD1 or VDD2 4.6 3.2 mA mA 5 MHz logic signal freq. 5 MHz logic signal freq. 1.0 1.6 mA mA DC to 1 MHz logic signal freq. DC to 1 MHz logic signal freq. 1.7 1.3 mA mA DC to 1 MHz logic signal freq. DC to 1 MHz logic signal freq.
IIA, IIB VIH VIL
-10 0.7 x (VDD1 or VDD2)
0.3 x (VDD1 or VDD2) 0.8 0.4 (VDD1 or VDD2) - 0.1 (VDD1 or VDD2) - 0.5
VOAH, VOBH
Logic Low Output Voltages
VOAL, VOBL
(VDD1 or VDD2) VDD1, VDD2 - 0.2 0.0 0.04 0.2
IOx = -20 A, VIx = VIxH IOx = -4 mA, VIx = VIxH IOx = 20 A, VIx = VIxL IOx = 400 A, VIx = VIxL IOx = 4 mA, VIx = VIxL CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels
SWITCHING SPECIFICATIONS Minimum Pulse Width 2 Maximum Data Rate 3 Propagation Delay 4 Pulse Width Distortion, |tPLH - tPHL|4 Change vs. Temperature Propagation Delay Skew 5 Channel-to-Channel Matching 6 Output Rise/Fall Time (10% to 90%) 5 V/3 V Operation 3 V/5 V Operation
PW tPHL, tPLH PWD
Rev. A | Page 8 of 20
ADUM3210
Parameter Common-Mode Transient Immunity at Logic High Output 7 Common-Mode Transient Immunity at Logic Low Output7 Refresh Rate 5 V/3 V Operation 3 V/5 V Operation Input Dynamic Supply Current, per Channel 8 5 V/3 V Operation 3 V/5 V Operation Output Dynamic Supply Current, per Channel8 5 V/3 V Operation 3 V/5 V Operation
1
Symbol |CMH| |CML| fr
Min 25 25
Typ 35 35
Max
Unit kV/s kV/s
Test Conditions VIx = VDD1, VDD2, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
1.2 1.1 IDDI (D) 0.19 0.10 IDDO (D) 0.03 0.05
Mbps Mbps mA/Mbps mA/Mbps mA/Mbps mA/Mbps
The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 4 through Figure 6 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 7 and Figure 8 for total VDD1 and VDD2 supply currents as a function of data rate. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 4 through Figure 6 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate.
Rev. A | Page 9 of 20
ADUM3210
PACKAGE CHARACTERISTICS
Table 6.
Parameter Resistance (Input-to-Output) 1 Capacitance (Input-to-Output)1 Input Capacitance IC Junction-to-Case Thermal Resistance, Side 1 IC Junction-to-Case Thermal Resistance, Side 2
1
Symbol RI-O CI-O CI JCI JCO
Min
Typ 1012 1.0 4.0 46 41
Max
Unit pF pF C/W C/W
Test Conditions f = 1 MHz Thermocouple located at center of package underside
The device is considered a 2-terminal device; Pin 1 through Pin 4 are shorted together, and Pin 5 through Pin 8 are shorted together.
REGULATORY INFORMATION
The ADUM3210 is approved by the organizations listed in Table 7. Table 7.
UL Recognized under UL 1577 Component Recognition Program 1 Single/Basic 2500 V rms Isolation Voltage CSA Approved under CSA Component Acceptance Notice #5A VDE Certified according to DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 2 Reinforced insulation, 560 V peak
File E214100
1 2
Basic insulation per CSA 60950-1-03 and IEC 60950-1, 400 V rms (566 V peak) maximum working voltage Functional insulation per CSA 60950-1-03 and IEC 60950-1, 800 V rms(1131 V peak) maximum working voltage File 205078
File 2471900-4880-0001
In accordance with UL 1577, each ADUM3210 is proof tested by applying an insulation test voltage 3000 V rms for 1 second (current leakage detection limit = 5 A). In accordance with DIN V VDE V 0884-10, each ADUM3210 is proof tested by applying an insulation test voltage 1050 V peak for 1 second (partial discharge detection limit = 5 pC). An asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 8.
Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group Symbol L(I01) L(I02) Value 2500 4.90 min 4.01 min 0.017 min >175 IIIa Unit V rms mm mm mm V Conditions 1-minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Insulation distance through insulation DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1)
CTI
Rev. A | Page 10 of 20
ADUM3210
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
These isolators are suitable for reinforced isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The asterisk (*) marking on the package denotes DIN V VDE V 0884-10 approval for a 560 V peak working voltage. Table 9.
Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage 150 V rms For Rated Mains Voltage 300 V rms For Rated Mains Voltage 400 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input-to-Output Test Voltage, Method B1 Input-to-Output Test Voltage, Method A After Environmental Tests Subgroup 1 After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Safety-Limiting Values Case Temperature Side 1 Current Side 2 Current Insulation Resistance at TS Conditions Symbol Characteristic I to IV I to III I to II 40/105/21 2 560 1050 Unit
VIORM x 1.875 = VPR, 100% production test, tm = 1 sec, partial discharge < 5 pC VIORM x 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC VIORM x 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC Transient overvoltage, tTR = 10 sec Maximum value allowed in the event of a failure (see Figure 2)
VIORM VPR VPR
V peak V peak
896 672 VTR 4000
V peak V peak V peak
VIO = 500 V
TS IS1 IS2 RS
150 150 160 >109
C mA mA
200 180
RECOMMENDED OPERATING CONDITIONS
Table 10.
SIDE #1 SIDE #2
SAFETY-LIMITING CURRENT (mA)
160 140 120 100 80 60 40 20 0 50 100 150 CASE TEMPERATURE (C) 200
06866-002
Parameter Operating Temperature ADUM3210BR ADUM3210TR Supply Voltages 1 ADUM3210BR ADUM3210TR Input Signal Rise and Fall Times
1
Symbol TA TA VDD1, VDD2 VDD1, VDD2
Min -40 -40 2.7 3
Max +105 +125 5.5 5.5 1
Unit C C V V ms
0
Figure 2. Thermal Derating Curve, Dependence of Safety-Limiting Values on Case Temperature, per DIN V VDE V 0884-10
All voltages are relative to their respective ground. See the DC Correctness and Magnetic Field Immunity section for information on immunity to external magnetic fields.
Rev. A | Page 11 of 20
ADUM3210 ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25C, unless otherwise noted. Table 11.
Parameter Storage Temperature Ambient Operating Temperature Supply Voltages1 Input Voltage1, 2 Output Voltage1, 2 Average Output Current, per Pin3 Common-Mode Transients4
1 2
Symbol TST TA VDD1, VDD2 VIA, VIB VOA, VOB IO CMH, CML
Min -55 -40 -0.5 -0.5 -0.5 -35 -100
Max +150 +105 +7.0 VDDI + 0.5 VDDO + 0.5 +35 +100
Unit C C V V V mA kV/s
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
All voltages are relative to their respective ground. VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. 3 See Figure 2 for information on maximum allowable current for various temperatures. 4 Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the Absolute Maximum Rating can cause latch-up or permanent damage.
Table 12. Maximum Continuous Working Voltage1
Parameter AC Voltage, Bipolar Waveform AC Voltage, Unipolar Waveform Functional Insulation Basic Insulation DC Voltage Functional Insulation Basic Insulation
1
Max 565 1131 560 1131 560
Unit V peak V peak V peak V peak V peak
Constraint 50-year minimum lifetime Maximum approved working voltage per IEC 60950-1 Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10 Maximum approved working voltage per IEC 60950-1 Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
Table 13. Truth Table (Positive Logic)
VIA Input H L H L X X VIB Input H L L H X X VDD1 State Powered Powered Powered Powered Unpowered Powered VDD2 State Powered Powered Powered Powered Powered Unpowered VOA Output H L H L L Indeterminate VOB Output H L L H L Indeterminate Notes
Outputs return to the input state within 1 s of VDDI power restoration Outputs return to the input state within 1 s of VDDO power restoration
Rev. A | Page 12 of 20
ADUM3210 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD1 1 VIA 2 VIB 3
8
VDD2 VOA
06866-003
ADUM3210
7
6 VOB TOP VIEW GND1 4 (Not to Scale) 5 GND2
Figure 3. Pin Configuration
Table 14. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 Mnemonic VDD1 VIA VIB GND1 GND2 VOB VOA VDD2 Description Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V. Logic Input A. Logic Input B. Ground 1. Ground reference for Isolator Side 1. Ground 2. Ground reference for Isolator Side 2. Logic Output B. Logic Output A. Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.
Rev. A | Page 13 of 20
ADUM3210 TYPICAL PERFORMANCE CHARACTERISTICS
10
20
8
CURRENT/CHANNEL (mA)
15
6
CURRENT (mA)
10
4 5V
5V 5
2
3V
3V
06866-004
0
10 20 DATA RATE (Mbps)
30
0
10 20 DATA RATE (Mbps)
30
Figure 4. Typical Input Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation
4
4
Figure 7. Typical VDD1 Supply Current vs. Data Rate for 5 V and 3 V Operation
CURRENT/CHANNEL (mA)
3
3
CURRENT (mA)
5V 2
2 5V 1 3V
06866-005
3V 1
0
10 20 DATA RATE (Mbps)
30
0
10 20 DATA RATE (Mbps)
30
Figure 5. Typical Output Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation (No Output Load)
4
Figure 8. Typical VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation
CURRENT/CHANNEL (mA)
3
2 5V
1 3V
0
10 20 DATA RATE (Mbps)
30
Figure 6. Typical Output Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation (15 pF Output Load)
06866-006
0
Rev. A | Page 14 of 20
06866-008
0
0
06866-007
0
0
ADUM3210 APPLICATIONS INFORMATION
PC BOARD LAYOUT
The ADUM3210 digital isolator requires no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins. The capacitor value should be between 0.01 F and 0.1 F. The total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The propagation delay to a logic low output can differ from the propagation delay to a logic high output.
INPUT (VIx) 50%
OUTPUT (VOx)
50%
System-level ESD reliability (for example, per IEC 61000-4-x) is highly dependent on system design, which varies widely by application. The ADUM3210 incorporates many enhancements to make ESD reliability less dependent on system design. The enhancements include: * * * ESD protection cells added to all input/output interfaces. Key metal trace resistances reduced using wider geometry and paralleling of lines with vias. The SCR effect inherent in CMOS devices minimized by use of guarding and isolation technique between PMOS and NMOS devices. Areas of high electric field concentration eliminated using 45 corners on metal traces. Supply pin overvoltage prevented with larger ESD clamps between each supply pin and its respective ground.
Figure 9. Propagation Delay Parameters
Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signal timing is preserved. Channel-to-channel matching refers to the maximum amount that the propagation delay differs between channels within a single ADUM3210 component. Propagation delay skew refers to the maximum amount that the propagation delay differs between multiple ADUM3210 components operating under the same conditions.
* *
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions of more than 2 s at the input, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no internal pulses for more than about 5 s, the input side is assumed to be unpowered or nonfunctional, in which case, the isolator output is forced to a default state (see Table 13) by the watchdog timer circuit. The ADUM3210 is immune to external magnetic fields. The limitation on the ADUM3210 magnetic field immunity is set by the condition in which induced voltage in the transformer receiving coil is sufficiently large to either falsely set or reset the decoder. The following analysis defines the conditions under which this can occur. The 3 V operating condition of the ADUM3210 is examined because it represents the most susceptible mode of operation.
While the ADUM3210 improves system-level ESD reliability, it is no substitute for a robust system-level design. For detailed recommendations on board layout and system-level design, see AN-793 Application Note, ESD/Latch-Up Considerations with iCoupler Isolation Products.
Rev. A | Page 15 of 20
06866-009
SYSTEM-LEVEL ESD CONSIDERATIONS AND ENHANCEMENTS
tPLH
tPHL
ADUM3210
MAXIMUM ALLOWABLE CURRENT (kA)
The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, therefore establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by V = (-d/dt) rn2, n = 1, 2, ... , N where: is the magnetic flux density (gauss). N is the number of turns in the receiving coil. rn is the radius of the nth turn in the receiving coil (cm). Given the geometry of the receiving coil in the ADUM3210 and an imposed requirement that the induced voltage is at most 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated, as shown in Figure 10.
100
1000 DISTANCE = 1m 100
10 DISTANCE = 100mm 1 DISTANCE = 5mm 0.1
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 11. Maximum Allowable Current for Various Current-to-ADUM3210 Spacings
MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kgauss)
10
1
Note that at combinations of strong magnetic fields and high frequencies, any loops formed by PCB traces may induce sufficiently large error voltages to trigger the threshold of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.
POWER CONSUMPTION
0.1
0.01
The supply current at a given channel of the ADUM3210 isolator is a function of the supply voltage, channel data rate, and channel output load. For each input channel, the supply current is given by
06866-010
0.001 1k
10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz)
100M
IDDI = IDDI (Q) IDDI = IDDI (D) x (2f - fr) + IDDI (Q) IDDO = IDDO (Q)
-3
f 0.5fr f > 0.5fr f 0.5fr
Figure 10. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event were to occur during a transmitted pulse (and had the worst-case polarity), it would reduce the received pulse from >1.0 V to 0.75 V, which is still well above the 0.5 V sensing threshold of the decoder. The preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the ADUM3210 transformers. Figure 11 expresses these allowable current magnitudes as a function of frequency for selected distances. As shown, the ADUM3210 is immune and can be affected only by extremely large currents operated at a high frequency and very close to the component. For the 1 MHz example, one would have to place a 0.5 kA current 5 mm away from the ADUM3210 to affect the component's operation.
For each output channel, the supply current is given by IDDO = (IDDO (D) + (0.5 x 10 ) x CLVDDO) x (2f - fr) + IDDO (Q) f > 0.5fr where: IDDI (D), IDDO (D) are the input and output dynamic supply currents per channel (mA/Mbps). CL is the output load capacitance (pF). VDDO is the output supply voltage (V). f is the input logic signal frequency (MHz, half of the input data rate, NRZ signaling). fr is the input stage refresh rate (Mbps). IDDI (Q), IDDO (Q) are the specified input and output quiescent supply currents (mA). To calculate the total IDD1 and IDD2 supply current, the supply currents for each input and output channel corresponding to IDD1 and IDD2 are calculated and totaled. Figure 4 provides per-channel input supply currents as a function of data rate. Figure 5 and Figure 6 provide per-channel output supply currents as a function of data rate for an unloaded output condition and for a 15 pF output condition, respectively. Figure 7 and Figure 8 provide total IDD1 and IDD2 supply current as a function of data rate.
Rev. A | Page 16 of 20
06866-011
0.01
ADUM3210
INSULATION LIFETIME
All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADUM3210. Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. The values shown in Table 12 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition, and the maximum CSA/VDE approved working voltages. In many cases, the approved working voltage is higher than 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases. The insulation lifetime of the ADUM3210 depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 12, Figure 13, and Figure 14 illustrate these different isolation voltage waveforms. A bipolar ac voltage environment is the most stringent. The goal of a 50-year operating lifetime under the ac bipolar condition determines the Analog Devices recommended maximum working voltage. In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows operation at higher working voltages while still achieving a 50-year service life. The working voltages listed in Table 12 can be applied while maintaining the 50-year minimum lifetime provided that the voltage conforms to either the unipolar ac or dc voltage cases. Any cross-insulation voltage waveform that does not conform to Figure 13 or Figure 14 should be treated as a bipolar ac waveform, and its peak voltage should be limited to the 50-year lifetime voltage value listed in Table 12. Note that the voltage presented in Figure 13 is shown as sinusoidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V.
RATED PEAK VOLTAGE 0V
06866-012
Figure 12. Bipolar AC Waveform
RATED PEAK VOLTAGE
06866-013
0V
Figure 13. Unipolar AC Waveform
RATED PEAK VOLTAGE
06866-014
0V
Figure 14. DC Waveform
Rev. A | Page 17 of 20
ADUM3210 OUTLINE DIMENSIONS
5.00 (0.1968) 4.80 (0.1890)
8
5 4
4.00 (0.1574) 3.80 (0.1497)
1
6.20 (0.2441) 5.80 (0.2284)
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE
1.75 (0.0688) 1.35 (0.0532)
0.50 (0.0196) 0.25 (0.0099) 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157)
45
0.51 (0.0201) 0.31 (0.0122)
COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 15. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters (inches)
ORDERING GUIDE
Model ADUM3210BRZ 2 ADUM3210BRZ-RL72 ADUM3210TRZ2 ADUM3210TRZ-RL72
1 2
Number of Inputs, VDD1 Side 2 2 2 2
Number of Inputs, VDD2 Side 0 0 0 0
Maximum Data Rate (Mbps) 10 10 10 10
Maximum Propagation Delay, 5 V (ns) 50 50 50 50
Maximum Pulse Width Distortion (ns) 40 40 40 40
012407-A
Temperature Range -40C to +105C -40C to +105C -40C to +125C -40C to +125C
Package Option 1 R-8 R-8 R-8 R-8
R-8 = 8-lead narrow body SOIC_N. Z = RoHS Compliant Part.
Rev. A | Page 18 of 20
ADUM3210 NOTES
Rev. A | Page 19 of 20
ADUM3210 NOTES
(c)2007-2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06866-0-9/08(A)
Rev. A | Page 20 of 20

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